The present invention relates to a disk cache control method and a rotary storage device, and in particular, to a disk cache control technology effectively applicable to a magnetic disk subsystem or the like to be connected as an external storage device to an information processing apparatus.
For example, in the field of information processing technology in which distributed computer processing utilizes a disk storage media for a storage device, there has been required a disk subsystem which is compatible with a high-speed random data processing. In this case, to prevent elongation of the mean processing time associated with a mechanical seek time and a latency in the random read and write operations requested from a higher-level apparatus, such as a central processing unit (CPU), to a disk, there has been employed in a data transfer path to the disk unit a cache memory in the form of a semiconductor memory, and having a higher operation speed as compared with the disk storage, thereby increasing the processing speed. However, since the semiconductor memory has a bit cost which is significantly higher than that of the disk medium, the feasible capacity of the cache memory is limited in the present state of the art.
FIG. 23 shows the general configuration of an example of a disk device to be operated in association with a cache memory. When the disk device receives a command or instruction for the writing of data via an upper-level interface circuit 102 from a host computer 101, a CPU 107 writes the data via a cache controller 103 in a cache memory 104 at an address specified by the instruction. When the disk device receives a read instruction from the host computer 101, the CPU 107 references a cache control table in the cache controller 103. If the data exists in the cache memory 104, namely, in a case of a "cache hit" the CPU 107 activates the cache controller 103 to transmit the data from the cache memory 104 to the host computer 101.
If the data requested by the read instruction is missing in the cache memory 104, namely, in the case of a "cache miss" the CPU 107 activates a disk controller 105 to access the disk devices 1061 to 106N (N may be "one" depending on cases) to read data from the pertinent address so as to store the obtained data via the cache controller 103 in the cache memory 104 and to concurrently transfer the read data via the upper-level interface circuit 102 to the host computer 101.
There may also be considered a method in which operations of the upper-level interface circuit 102, the cache controller 103, and the disk controller 105 are autonomously conducted without using instructions from the CPU 107 and without necessitating the monitoring operation of the CPU 107.
In the write operation, even when a cache hit occurs for each access request (hit rate=100%) in the cache memory 104, it is necessary to finally write each data item in the destination storage position in the disk devices 1061 to 106N in a random fashion.
Further, in the case where a miss hit occurs due to insufficient capacity of the cache memory 104 or in a case where write cache data is written on a disk, random processing in the disk devices 1061 to 106N also must be performed.
On the other hand, in JP-A-60-258661 entitled "Cache Memory Controller", there have been described a scheme for utilization of a cache memory to minimize the number of accesses to disks and an efficient method of controlling the cache memory. However, the control operation for reading data in the event of a miss hit of the cache, the control operation to be effected when power is interrupted, and the control operation for writing cache data on a disk in response to a processing request from a higher-level apparatus are substantially identical to those employed in the example of FIG. 23 in that the access operations are actually conducted according to random addresses on the disks.
In the prior art referenced above, when the capacity of the cache memory is increased to improve the hit rate, the cost of the apparatus inevitably increases substantially. Moreover, in a case where a disk write operation is required due to a miss hit in the cache memory during a data write operation, there occurs a random access to the disk. Namely, the seek time and the latency remain as relevant factors, which leads to a problem of a longer processing time.
For example, in the case where the cache capacity is 16 megabytes (MB) and the data processing unit includes 16 kilobytes (KB), when it is desired to save data in a termination processing of the system, there occur 1000 input/output (I/O) operations. Each I/O operation takes a period of time represented as follows. ##EQU1## Assuming that the values of the above items are applied to a 5-inch disk device with a rotary speed of 5400 rotations per minute (RPM), as generally used, the I/O processing time Tpc of each I/O operation is as follows. ##EQU2##
In the disk device with a rotary speed of 5400 rpm, one disk rotation takes 11.1 ms. Half the rotation period is consumed by the latency. In a case where each sector includes 512 bytes and each track has 80 sectors by way of example, the period of time required to access 16 kilobytes (=32 sectors) is expressed as 32/80 x (one disk rotation time).
In consequence, the processing time necessary for 1000 I/O operations is 23.8 seconds in this apparatus.